library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.FAW_TYPES.all;

entity TargetSampledPointsShiftRegisterS is
    Port ( clk_tspsrs : in  STD_LOGIC;
           data_in_tspsrs : in  STD_LOGIC_VECTOR (7 downto 0);
           we_tspsrs : in  TARGET_SR_ENABLE_ROWS;
           oe_tspsrs : in  TARGET_SR_ENABLE_BUS;
           sclear_tspsrs : in  STD_LOGIC;
                          oe_tspsrs_rows : in TARGET_SR_ENABLE_ROWS;
           data_out_tspsrs : out  TSPSRC_SR_DATA_BUS);
end TargetSampledPointsShiftRegisterS;

architecture Archi of TargetSampledPointsShiftRegisterS is

        component TSP_ShiftRegister is
                Port ( 
                          clk_tspsr : in  STD_LOGIC;
           data_in_tspsr : in  STD_LOGIC_VECTOR (7 downto 0);
                          we_tspsr : in std_logic;
           oe_tspsr : in STD_LOGIC_VECTOR (W-1 downto 0);
                          oe_tspsr_row : in STD_LOGIC;
           sclear_tspsr : in  STD_LOGIC;
                          data_out_tspsr : out  TSPSR_SR_DATA_BUS
                          );
        end component;

begin

        ShiftRegisters : for i in 0 to RSPSRC_SR_REGISTERS-1 generate
                ShiftRegister: TSP_ShiftRegister
                port map(
                        clk_tspsr=>clk_tspsrs,
                        data_in_tspsr=>data_in_tspsrs,
                        we_tspsr=>we_tspsrs(i),
                        oe_tspsr=>oe_tspsrs(i),
                        oe_tspsr_row=>oe_tspsrs_rows(i),
                        sclear_tspsr=>sclear_tspsrs,
                        data_out_tspsr=>data_out_tspsrs(i)
                );
        end generate ShiftRegisters;


end Archi;